Citation
Tan, Kok Siang and Sulaiman, Mohd Shahiman and Chuah, Hean Teik and Sachdev, Manoj (2007) Design of high-speed clock and data recovery circuits. Analog Integrated Circuits and Signal Processing, 52 (1-2). pp. 15-23. ISSN 0925-1030, 1573-1979 Full text not available from this repository.
Official URL: http://dx.doi.org/10.1007/s10470-007-9093-1
Abstract
This article describes the various architectures for a high-speed clock and data recovery (CDR) circuit. Following a brief introduction of clock and data recovery circuit, a phase detection circuit, one of the most critical blocks in a CDR that determines not only the performance but also the CDR architecture, is addressed. The descriptions start with the most basic XOR logic up to the phase-frequency detector circuit. Trade-offs of each of the phase detectors are outlined. Two types of dual loop CDR architecture are briefly introduced. Finally, full-rate and half rate CDR architectures are described.
Item Type: | Article |
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Subjects: | T Technology > T Technology (General) Q Science > QA Mathematics > QA71-90 Instruments and machines > QA75.5-76.95 Electronic computers. Computer science |
Divisions: | Faculty of Engineering and Technology (FET) |
Depositing User: | Ms Suzilawati Abu Samah |
Date Deposited: | 27 Sep 2011 02:21 |
Last Modified: | 29 Dec 2020 17:25 |
URII: | http://shdl.mmu.edu.my/id/eprint/3029 |
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