Citation

Shivakumar, Vishnupriya and Senthilpari, Chinnaiyan and Yusoff, Zubaida (2021) Design of a 1.9 GHz low-power LFSR Circuit using the Reed-Solomon Algorithm for Pseudo-Random Test Pattern Generation. International Journal of Integrated Engineering (IJIE), 13 (6). pp. 220-232. ISSN 2229-838X, 2600-7916

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Abstract

A linear feedback shift register (LFSR) has been frequently used in the Built-in Self-Test (BIST) designs for the pseudo-random test pattern generation. The volume of the test patterns and test power dissipation are the key features in the large complex designs. The objective of this paper is to propose a new LFSR circuit based on the proposed Reed-Solomon (RS) algorithm. The RS algorithm is created by considering the factors of the maximum length test pattern with a minimum distance over the time. Also, it has achieved an effective generation of test patterns over a stage of complexity order O (m log2m), where m denotes the total number of message bits. We analyzed our RS LFSR mathematically using the feedback polynomial function for an area-sensitive design. However, the bit-wise stages of the proposed RS LFSR are simulated using the TSMC 130 nm IC design tool in the Mentor Graphics platform. Experimental results showed that the proposed LFSR achieved the effective pseudo-random test patterns with a low-test power dissipation (25.13 µW). Ultimately, the circuit has operated in the highest operating frequency (1.9 GHz) environment.

Item Type:	Article
Uncontrolled Keywords:	Algorithms, Reed-Solomon (RS), Galois Field (GF), Linear Feedback Shift Register (LFSR)
Subjects:	Q Science > QA Mathematics > QA71-90 Instruments and machines > QA75.5-76.95 Electronic computers. Computer science
Divisions:	Faculty of Engineering (FOE)
Depositing User:	Ms Nurul Iqtiani Ahmad
Date Deposited:	03 Nov 2021 08:15
Last Modified:	03 Nov 2021 08:15
URII:	http://shdl.mmu.edu.my/id/eprint/9733

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