VHDL modelling of the open short tester


Pang, Wai Leong and Chew, Kok Wai and Choong, Florence Chiao Mei and Chan, C. L. (2007) VHDL modelling of the open short tester. In: 6th WSEAS International Conference on Instrumentation, Measurement, Circuits and Systems/7th WSEAS International Conference on Robotics, Control and Manufacturing Technology, 15-17 April 2007, Hangzhou, China.

[img] Text
VHDL modelling of the open short tester.pdf
Restricted to Repository staff only

Download (1MB)


IC (Integrated Circuitry) testing requires the very advanced and sophisticated Advance Test Equipment (ATE) that costs multi million USD. The cost of IC testing is increasing yearly and it will exceed the cost of manufacturing in future. The manufacturers are interested to lower down the manufacturing cost. Low cost tester is one of the options to reduce the manufacturing cost. The low cost FPGA realization of Open/Short Test on IC is introduced to reduce the IC test cost. The open short test is selected, because it is the first IC test. The Very High Speed Integrated Circuit Hardware Description Language (VHDL) is used to model the Open/Short Test on IC and the design is capable to perform the open/short test.

Item Type: Conference or Workshop Item (Paper)
Subjects: T Technology > T Technology (General)
Q Science > QA Mathematics > QA71-90 Instruments and machines > QA75.5-76.95 Electronic computers. Computer science
Divisions: Faculty of Engineering and Technology (FET)
Depositing User: Ms Suzilawati Abu Samah
Date Deposited: 06 Oct 2011 00:09
Last Modified: 22 Apr 2021 16:40
URII: http://shdl.mmu.edu.my/id/eprint/3190


Downloads per month over past year

View ItemEdit (login required)