A fully-integrated 5 Gbit/s CMOS clock and data recovery circuit


Tan, Kok Siang and Sulaiman, Mohd Shahiman and Ibne, Mamun Reaz and Chuah, Hean Teik and Sachdev, Manoj (2007) A fully-integrated 5 Gbit/s CMOS clock and data recovery circuit. Analog Integrated Circuits and Signal Processing, 51 (2). 101-109 . ISSN 0925-1030, 1573-1979

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A fully-integrated 5 Gb/s PLL-based clock and data recovery circuit based on a linear half-rate phase detector (PD) architecture is presented. Data retiming performed by the linear PD provides practically no systematic offset for the operating frequency of interest. The circuit was designed in a 0.18 mu m CMOS process and occupies an active area of 0.2 x 0.32 mm(2). The CDR exhibits an RMS jitter of +/- 1.2 ps and a peak-to-peak jitter of 5 ps. The power dissipation is 97 mW from a 1.8 V supply.

Item Type: Article
Subjects: T Technology > T Technology (General)
Q Science > QA Mathematics > QA71-90 Instruments and machines > QA75.5-76.95 Electronic computers. Computer science
Divisions: Faculty of Engineering and Technology (FET)
Depositing User: Ms Suzilawati Abu Samah
Date Deposited: 29 Sep 2011 04:03
Last Modified: 29 Dec 2020 17:53
URII: http://shdl.mmu.edu.my/id/eprint/3065


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