A study and design of CMOS H-Tree clock distribution network in system-on-chip


Loo, Wei-Khee and Tan, Kok-Siang and Teh, Ying-Khai (2009) A study and design of CMOS H-Tree clock distribution network in system-on-chip. In: IEEE 8th International Conference on ASIC Location: Changsha, PEOPLES R CHINA, OCT 20-23, 2009 , IEEE Beijing Sect; Fudan Univ; IEEE China Council; Natl Univ Def Tech; IEEE CAS, IEEE SSCS; Chinese Inst Elect.

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A design of a low skew clock distribution network is presented based on the TSMC 0.18 mu m CMOS technology. This work first investigated various aspects in designing a clock distribution network. After that, the design methodology for the chosen H-Tree clock network topology is presented. A series of design performance analyses such as clock delay, skew, rise and fall time, supply voltage and temperature variations and power consumption were compared for both pre-layout and post-layout simulation results. Pre-layout and post-layout simulation results validated the 3-segment pi-model. The clock network designed is able to operate up to maximum clock speed of 1.1GHz for a 1 x 1 mm(2) chip with zero skew.

Item Type: Conference or Workshop Item (Paper)
Subjects: T Technology > T Technology (General)
Q Science > QA Mathematics > QA71-90 Instruments and machines > QA75.5-76.95 Electronic computers. Computer science
Divisions: Faculty of Engineering and Technology (FET)
Depositing User: Ms Suzilawati Abu Samah
Date Deposited: 23 Sep 2011 03:18
Last Modified: 23 Sep 2011 03:18
URII: http://shdl.mmu.edu.my/id/eprint/1922


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