Citation

Souk, Abdulrahman Cheikh and Lini, Lee (2025) Challenges in FPGA-Based AI Accelerator with RISC-V Integration. In: 2024 Multimedia University Engineering Conference (MECON), 23-25 July 2024, Cyberjaya, Malaysia.

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Abstract

The rising complexity of machine learning (ML) applications has increased the demand for efficient artificial intelligence (AI) hardware. While Graphical Processing Units (GPUs) and Tensor Processing Units (TPUs) are widely used for AI acceleration, they face challenges such as high cost, limited flexibility, and poor energy efficiency. Field Programmable Gate Arrays (FPGAs) have emerged as a promising alternative, especially for edge computing, due to their low power consumption and reconfigurability. Integrating FPGAs with RISC-V, an open-source instruction set architecture (ISA), offers further customization and performance benefits, drawing growing research interest. This paper reviews the current landscape of FPGA-based AI accelerators with RISC-V integration, identifying key technical challenges including hardware design complexity, resources limitations, and toolchain gaps, along with other issues discussed in the paper. Furthermore, we outline future research directions to enhance efficiency, programmability, and deployment viability for next-generation edge AI systems. Our analysis serves as a roadmap for researchers and practitioners aiming to harness the full potential of FPGA-RISC-V acceleratio

Item Type:	Conference or Workshop Item (Paper)
Uncontrolled Keywords:	AI accelerator, Challenges
Subjects:	Q Science > QA Mathematics > QA71-90 Instruments and machines > QA75.5-76.95 Electronic computers. Computer science
Divisions:	Faculty of Artificial Intelligence & Engineering (FAIE)
Depositing User:	Ms Rosnani Abd Wahab
Date Deposited:	17 Mar 2026 07:16
Last Modified:	17 Mar 2026 08:02
URII:	http://shdl.mmu.edu.my/id/eprint/15524

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