Citation

Senthilpari, Chinnaiyan and Velrajkumar, P. and ., Diwakar and Francisca, Joseph Sheela and ., Gautam (2020) Design A Low Power And High Throughput Error Detection And Data Correction Architecture By Razor II Method. PalArch’s Journal of Archaeology of Egypt/Egyptology, 17 (9). pp. 4393-4410. ISSN 1567-214X

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Abstract

The proposed error detection and correction circuit designed due to the existing circuits accommodate the worst-case delay. To prevent Error in the system, detect and determine violation to maintain correctness to help on the fly mechanisms. The proposed circuit is to present speculative error detection technique along with an error recovery mechanism. Circuits are wanted to oblige the delay and to get to be deficient in their execution. To enhance the execution, they oblige fly system to forestall, identify and correct errors. In this paper, low power speculative error detection and error recovery architecture are PJAEE, 17 (9) (2020) 4394 to be developed. The main aim of the circuit is to reduce delay, power and area. This paper demonstrates their ability to operate under worst-case accommodation. The proposed error correction and detection circuit give 226nW, propagation delay 1ps, throughput 792MHz..

Item Type:	Article
Uncontrolled Keywords:	Error-recovery system, Error-Detection, Razor, Propagation delay, Power dissipation.
Subjects:	T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK452-454.4 Electric apparatus and materials. Electric circuits. Electric networks
Divisions:	Faculty of Computing and Informatics (FCI)
Depositing User:	Ms Rosnani Abd Wahab
Date Deposited:	05 Oct 2021 01:29
Last Modified:	05 Oct 2021 01:36
URII:	http://shdl.mmu.edu.my/id/eprint/8468

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