Citation

Singh, Ajay Kumar and Saadatzi, Mohammadsadegh and Venkata Seshaiah, Chinthakunta (2016) Design of Peripheral Circuits for the Implementation of Memory Array Using Data-Aware (DA) SRAM Cell in 65 nm CMOS Technology for Low Power Consumption. Journal of Low Power Electronics, 12 (1). pp. 9-20. ISSN 1546-1998

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Abstract

This paper presents the design of the peripheral circuits required to implement a memory array using data-aware (DA) SRAM cell. We used global signal generator circuits to reduce the area overhead. The global generator circuits are connected to their local counterparts through NMOS pass transistors. The column based approach is adopted in which write signal is routed parallel to bitline BL because write signal has to track BL. The adopted design approach in this thesis reduces the number of transistors as well as power consumption in the array. A feedback circuit has been proposed to maintain the data on the unselected cells of the selected row/column in the array due to toggle of the write signal during write operation. The proposed row/column circuitry saves more than 76% power and decodes the address 1.45 × faster than the conventional decoder. Compared to other memory architecture, the proposed architecture saves approximately 74% power at a given power supply and temperature.

Item Type:	Article
Uncontrolled Keywords:	Memory array, Peripheral circuits, Power consumption, Read/Write operation, SRAM cell
Subjects:	T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions:	Faculty of Engineering and Technology (FET)
Depositing User:	Ms Rosnani Abd Wahab
Date Deposited:	21 Nov 2017 09:08
Last Modified:	21 Nov 2017 09:08
URII:	http://shdl.mmu.edu.my/id/eprint/6503

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