Citation
Munusamy, Kumar and Kho, Daniel C. K. (2014) Transaction-based SoC design techniques for AMBA AXI4 bus interconnects using VHDL. In: 2014 11th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON). IEEE Xplore. ISBN 978-1-4799-2993-1
Text
Transaction-based SoC design techniques for AMBA AXI4 bus interconnects using VHDL.pdf Restricted to Repository staff only Download (290kB) |
Abstract
Transaction-level Modeling (TLM) and bus functional modeling (BFM) are widely-used techniques for functional verification of digital systems. Many modern systems-on-chip (SoC), network-on-chip (NoC), application-specific integrated circuit (ASIC), and field-programmable gate array (FPGA) designs have been verified using these techniques. However, transaction-based techniques have almost always [1]-[14] been used only for simulation of digital designs, and until recently, were not used to design physical hardware. This paper introduces a technique to develop transaction-based hardware. With this method, the same transaction-based model can both be simulated and synthesized to hardware. Several SoC/NoC subsystems can easily be interconnected in basically the same manner as how transaction-based simulation models are being written. This approach brings the benefits of transaction-based verification (TBV) to the hardware design engineers, resulting in a greater level of simplification for complex designs.
Item Type: | Book Section |
---|---|
Subjects: | T Technology > TK Electrical engineering. Electronics Nuclear engineering |
Divisions: | Faculty of Engineering (FOE) |
Depositing User: | Ms Nurul Iqtiani Ahmad |
Date Deposited: | 05 Sep 2014 02:43 |
Last Modified: | 05 Sep 2014 02:43 |
URII: | http://shdl.mmu.edu.my/id/eprint/5718 |
Downloads
Downloads per month over past year
Edit (login required) |