Citation

Pang, Wai Leong and Zareianjahromi, Seyed Arash and Phang, Swee King and Singh, Ajay Kumar and Tien Ng, Angie See and Chan, Kah-Yoong (2025) Design of a High Efficiency Single-Bit Full Adder Using Modified Gate Diffusion Input (MGDI) Technique. International Journal of Integrated Engineering, 17 (2). ISSN 2229838X

Text 8.+19128+95-112.pdf - Published Version Restricted to Repository staff only Download (960kB)

Abstract

Adders are essential parts of digital systems where critical design factors like size, power consumption, and latency are critical. This work presents a single-bit full adder based on the Modified Gate Diffusion Input (MGDI) technique to enhance the efficiency of these parameters. Extensive simulations were conducted using Mentor Graphics and 130nm CMOS technology, with extensive analysis comparing the proposed adder's performance against a standard CMOS adder across different voltage supply levels. The proposed adder utilizes only 8 transistors, significantly fewer than the 28 transistors required in conventional CMOS full adders. The MGDI technique proves highly effective, reducing power dissipation by 98.8%, area consumption by 18.1%, and propagation delay by 86.1%, while also simplifying circuit complexity. The suggested adder continuously exhibits decreasing power consumption and shorter propagation delay as the supply voltage rises, highlighting its appropriateness for high-performance, low-power applications. The reduced transistor count and minimized wiring complexity further establish the proposed adder as a compelling alternative to traditional CMOS designs.

Item Type:	Article
Uncontrolled Keywords:	Modified gate diffusion input, complimentary static CMOS, fu ll adder, delay, power consumption, area
Subjects:	T Technology > T Technology (General)
Divisions:	Faculty of Engineering (FOE)
Depositing User:	Ms Suzilawati Abu Samah
Date Deposited:	06 Oct 2025 02:04
Last Modified:	06 Oct 2025 02:08
URII:	http://shdl.mmu.edu.my/id/eprint/14663

Downloads

Edit (login required)