Citation

Ponnian, Jebashini (2023) Design a low-power and high-speed applications circuit using standard Gate Diffusion Input library cell. PhD thesis, Multimedia University.

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Abstract

Several monumental changes have occurred in today’s electronics, especially industrial and consumer devices. During the last decade, widespread deliberations have been specified to the usage of Gate Diffusion Input (GDI) networks in the design of digital core systems; however the logic design has been constructed using transistor-level. Till now there is no specific approach is available for synthesizing GDI circuit that incorporated the impact of signal arrangement and circuit technology. Creation of standard cell library for GDI technique becomes an utmost imperative. In this research work, a regimented synthesis algorithm have been proposed to minimize power and augment performance of the digital circuits through two approaches MUX based decomposition algorithm and Binary Decision Diagram (BDD). The primitive nodes are implemented by GDI logic and CMOS logic for level restoration circuit. This research work is targeted to design sub-micron GDI library which is suitable for the 180nm 6-metal layer CMOS n-well process which is offered by MOSIS. The synthesis of ISCAS Combinational bench mark circuit in CMOS, PTL and GDI technique is also examined in this work along with buffer inclusion procedure for GDI technique. The first objective is to modify the Gate Diffusion Input (GDI) Technique and to propose an unified signal connectivity model which provides full-swing support for power-speed efficient design. Proper level restoration circuit designed in all the basic primitive gates and the operation of the circuit explained in detail. The results shows the number of transistors reduced nearly 50 to 55% in MGDI circuits. The second objective defines to design a synthesisable library for circuit realisation in the Modified GDI Technique. creating a signal connectivity model for the GDI cell and its library creation. The third objective defines to design the Mathematical Models for delay and power characteristics for the synthesisable library for Modified GDI gates the electrical features of GDI logic to examine the complete characteristics of this technology. A unified power-delay model will be proposed for GDI logic to examine the device characteristics. By designing a new standard GDI library, this research work would increase the knowledge corridor of electronics. The comparison analysis shows that there is a 20-30% decrease for GDI in terms of power dissipation, delay and number of transistors with the existing technology CMOS. Thus the research work is productive and relevant to society in its knowledge domain and application area.

Item Type:	Thesis (PhD)
Additional Information:	Call No.: TK7868.L6 P66 2023
Uncontrolled Keywords:	Logic circuits
Subjects:	T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics
Divisions:	Faculty of Engineering (FOE)
Depositing User:	Ms Nurul Iqtiani Ahmad
Date Deposited:	29 Sep 2025 09:35
Last Modified:	29 Sep 2025 09:35
URII:	http://shdl.mmu.edu.my/id/eprint/14507

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