Low power and high speed 8x8 bit multiplier using non-clocked Pass Transistor Logic

Senthilpari, C. and Singh, Ajay Kumar and Diwakar, K. (2007) Low power and high speed 8x8 bit multiplier using non-clocked Pass Transistor Logic. In: International Conference on Intelligent and Advanced Systems, 25-28 NOV 2007 , Kuala Lumpur, MALAYSIA.

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Abstract

In this paper we have analyzed an 8-bit multiplier circuit using non clocked pass gate families with help of carry save multiplier (CSA) technique. The multiplier cell of the adder is designed by using pass transistors (n-transistors), p-transistors used as cross-coupled devices. The adder cell is designed by using multiplexing control input techniques. A combination of n- and p-transistors used on the mirror logic and inverters of full adder circuit. These multipliers are useful in the portable battery operated multimedia devices for energy efficient. The 8 bit multiplier circuit has been simulated using microwind3 VLSI layout CAD tool. We have analyzed the power dissipation, propagation delay, PDP and EPI (energy per instruction) and compared our results with other pass transistor logics as well as published results. From the simulated results it was found that the power dissipation and propagation delay are low in our designed non-clocked pass transistor logics. Our multiplier circuit shows a power dissipation improvement of 97.6% from Amir et.al and 46.30%, 23.24% and 0.15% from Rizwan et.al. Our multipliers gives better propagation delay compared to Rizwan et. al that are 89.56%, 88.39% and 88.31%

Item Type: Conference or Workshop Item (Paper)
Subjects: T Technology > T Technology (General)
Q Science > QA Mathematics > QA75.5-76.95 Electronic computers. Computer science
Divisions: Faculty of Engineering and Technology (FET)
Depositing User: Ms Suzilawati Abu Samah
Date Deposited: 18 Oct 2011 06:07
Last Modified: 18 Oct 2011 06:07
URI: http://shdl.mmu.edu.my/id/eprint/3161

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