Design of high-speed clock and data recovery circuits

Kok-Siang, Tan and Sulaiman, Mohd-Shahiman and Hean-Teik, Chuah and Sachdev, Manoj (2007) Design of high-speed clock and data recovery circuits. Analog Integrated Circuits and Signal Processing, 52 (1-2). pp. 15-23. ISSN 0925-1030

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Official URL: http://dx.doi.org/10.1007/s10470-007-9093-1

Abstract

This article describes the various architectures for a high-speed clock and data recovery (CDR) circuit. Following a brief introduction of clock and data recovery circuit, a phase detection circuit, one of the most critical blocks in a CDR that determines not only the performance but also the CDR architecture, is addressed. The descriptions start with the most basic XOR logic up to the phase-frequency detector circuit. Trade-offs of each of the phase detectors are outlined. Two types of dual loop CDR architecture are briefly introduced. Finally, full-rate and half rate CDR architectures are described.

Item Type: Article
Subjects: T Technology > T Technology (General)
Q Science > QA Mathematics > QA75.5-76.95 Electronic computers. Computer science
Divisions: Faculty of Engineering and Technology (FET)
Depositing User: Ms Suzilawati Abu Samah
Date Deposited: 27 Sep 2011 02:21
Last Modified: 27 Sep 2011 02:21
URI: http://shdl.mmu.edu.my/id/eprint/3029

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