Thirugnanam, Sargunam and Lim, Way Soong and Prabhu, Chinnaraj Munirathina and Singh, Ajay Kumar (2023) Energy-Efficient and Variability-Resilient 11T SRAM Design Using Data-Aware Read–Write Assist (DARWA) Technique for Low-Power Applications. Sensors, 23 (11). p. 5095. ISSN 1424-8220

Singh, Ajay Kumar and Tan, Chun Fui and Lim, Way Soong (2022) Drain current model for a hetero‐dielectric single gate tunnel field effect transistor ( HDSG TFET ). International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, 35 (3). ISSN 08943370

Sargunam, T. G. and Lim, Way Soong and Prabhu, Chinnaraj Munirathina and Singh, Ajay Kumar (2022) Process Tolerant and Power Efficient SRAM Cell for Internet of Things Applications. Computers, Materials & Continua, 72 (2). pp. 3425-3446. ISSN 1546-2226

Tan, Chun Fui and Singh, Ajay Kumar and Lim, Way Soong (2022) Study of Electrical Performance of Hetero-Dielectric Gate Tunnel Field Effect Transistor (HDG TFET): A Novel Structure for Future Nanotechnology. Journal of Engineering Technology and Applied Physics, 4 (1). pp. 35-39. ISSN 2682-8383

TG, Sargunam and Lim, Way Soong and Singh, Ajay Kumar and Prabhu, Chinnaraj Munirathina (2021) Design and Performance Analysis of Energy Efficient 11T SRAM (E2S11T) Cell for High Performance and Low Power Applications. In: 2021 IEEE International Workshop of Electronics, Control, Measurement, Signals and their application to Mechatronics (ECMSM), 21-22 June 2021, Liberec, Czech Republic.

TG, Sargunam and Lim, Way Soong and Prabhu, Chinnaraj Munirathina and Singh, Ajay Kumar (2021) Design and Statistical Analysis of Low Power Robust 13T Static Random Access Memory Cell for IoT Applications. In: 2021 IEEE Symposium on Industrial Electronics & Applications (ISIEA), 10-11 July 2021, Langkawi Island, Malaysia.

Singh, Ajay Kumar and Tan, Chun Fui (2021) Dual Metal Triple-gate-dielectric (DM_TGD) Tunnel Field Effect Transistor: A Novel Structure for Future Energy Efficient Device. Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering), 14 (6). pp. 683-693. ISSN 2352-0965

Tan, Chun Fui and Lim, Way Soong and Singh, Ajay Kumar (2021) Mathematical Modeling And Characterization Of Hetero-Gate-Dielectric Tunnel-Field Effect Transistor (Hgtfet). In: 2nd FET PG Engineering Colloquium Proceedings 2021, 1-15 Dec. 2021, Online Conference. (Unpublished)

Singh, Ajay Kumar and Tan, Chun Fui and Tan, Wilson Wee Xin (2020) Threshold voltage model for hetero-gate-dielectric tunneling field effect transistors. International Journal of Electrical and Computer Engineering (IJECE), 10 (2). pp. 1764-1771. ISSN 2088-8708

Chong, Peng Lean and Singh, Ajay Kumar and Kok, Swee Leong (2019) Characterization of Aloe Barbadensis Miller leaves as a potential electrical energy source with optimum experimental setup conditions. PLOS ONE, 14 (6). ISSN 1932-6203

Singh, Ajay Kumar (2019) Modeling of electrical behavior of undoped symmetric Double-Gate (DG) MOSFET using carrier-based approach. COMPEL: The International Journal for Computation and Mathematics in Electrical and Electronic Engineering, 38 (2). ISSN 0332-1649

Prabhu, Chinnaraj Munirathina and Singh, Ajay Kumar and TG, Sargunam (2019) Reliable data aware sram cell using FinFET technology. ARPN Journal of Engineering and Applied Sciences, 14 (8). pp. 1574-1577. ISSN 1819-6608

Singh, Ajay Kumar and Prabhu, Chinnaraj Munirathina and Sargunam, T. G. (2019) High Performance Data Aware (HPDA) SRAM cell for IoT applications. ARPN Journal of Engineering and Applied Sciences, 14 (1). pp. 91-94. ISSN 1819-6608

Sargunam, T. G. and Prabhu, Chinnaraj Munirathina and Singh, Ajay Kumar (2019) Design of High Performance FinFET SRAM Cell for Write Operation. In: Emerging Trends in Computing and Expert Technology. Lecture Notes on Data Engineering and Communications Technologies, 35 . Springer, Cham, pp. 908-914. ISBN 978-3-030-32149-9, 978-3-030-32150-5

Subramaniam, Shahmini and Singh, Ajay Kumar and Murthy, Gajula Ramana (2018) Design of power efficient stable 1-bit full adder circuit. IEICE Electronics Express, 15 (14). p. 20180552. ISSN 1349-2543

Singh, Ajay Kumar (2018) An analytical analysis of quantum capacitance in nano-scale single-wall carbon nano tube field effect transistor (CNTFET). International Journal of Nanoelectronics and Materials, 11 (3). pp. 249-262. ISSN 1985-5761

Singh, Ajay Kumar and Kumar, B. Naresh and Murhty, G. Ramana and Prabhu, Chinnaraj Munirathina (2017) A comprehensive analytical study of electrical properties of carbon nanotube field-effect transistor for future nanotechnology. International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, 31 (1). pp. 1-9. ISSN 08943370

Singh, Ajay Kumar and Saadatzi, Mohammadsadegh and Venkataseshaiah, Chinthakunta (2017) Design of a single-ended energy efficient data-dependent-write-assist dynamic (DDWAD) SRAM cell for improved stability and reliability. Analog Integrated Circuits and Signal Processing, 90 (2). pp. 411-426. ISSN 0925-1030; eISSN: 1573-1979

Singh, Ajay Kumar and Kumar, B. Naresh and Sheng, Gan Che (2017) A quantum correction based model for study of quantum confinement effects in nano-scale carbon nanotube field-effect transistor (CNTFET) under inversion condition. The European Physical Journal Applied Physics, 78 (1). p. 10101. ISSN 1286-0042

Singh, Ajay Kumar and Saadatzi, Mohammadsadegh and Venkata Seshaiah, Chinthakunta (2016) Design of Peripheral Circuits for the Implementation of Memory Array Using Data-Aware (DA) SRAM Cell in 65 nm CMOS Technology for Low Power Consumption. Journal of Low Power Electronics, 12 (1). pp. 9-20. ISSN 1546-1998

Prabhu, Chinnaraj Munirathina and Singh, Ajay Kumar (2015) Low-power reliable SRAM cell for write/read operation. IEICE Electronics Express, 11 (21). pp. 1-6. ISSN 1349-2543

Singh, Ajay Kumar and Seong, Mah Meng and Prahbu, C. M. R. (2014) A data aware 9T static random access memory cell for low power consumption and improved stability. International Journal of Circuit Theory and Applications, 42 (9). pp. 956-966. ISSN 1097-007X

Bhuvaneswari, Thangavel and Prasad, Vishnuvajjula Charan and Singh, Ajay Kumar (2013) Reversed signal propagation BDD based low-power pass-transistor logic synthesis. IEEJ Transactions on Electrical and Electronic Engineering, 8 (1). pp. 66-71.

Singh, Ajay Kumar (2011) An analytical study of undoped symmetric double gate MOSFET (SDG). International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, 24 (6). pp. 515-525. ISSN 08943370

Prabhu, C. M. R. and Singh, Ajay Kumar (2011) Low-power fast (LPF) SRAM cell for write/read operation. IEICE Electronics Express, 8 (18). pp. 1473-1478. ISSN 1349-2543

Bhuvaneswari, Thangavel and Prasad, Vishnuvajjula and Singh, Ajay Kumar and Senthilpari, Chinnaiyan (2011) Performance Analysis of Reversed Binary Decision Diagram Pass Transistor Logic Synthesis. International Journal of Circuit Theory and Applications, 41 (8). pp. 844-853. ISSN 00989886

Bhuvaneswari, T. and Prasad, V.C. and Singh, Ajay Kumar and Prasad, P.W.C. (2009) Weights Binary Decision Diagram (WBDD) and its application to Matrix Multiplication. In: Conference on Innovative Technologies in Intelligent Systems and Industrial Applications, JUL 25-26, 2009, Kuala Lumpur, MALAYSIA.

Diwakar, K. and Senthilpari, C. and Singh, Ajay Kumar (2008) Highly stable Delta-Sigma Modulator for industrial applications. IEICE Electronics Express, 5 (15). pp. 530-536. ISSN 1349-2543

Senthilpari, C. and Singh, Ajay Kumar and Diwakar, K. (2007) Low power and high speed 8x8 bit multiplier using non-clocked Pass Transistor Logic. In: International Conference on Intelligent and Advanced Systems, 25-28 NOV 2007 , Kuala Lumpur, MALAYSIA.

Senthilpari, Chinnaiyan and Singh, Ajay Kumar and Arokiasamy, A. (2007) Statistical analysis of power delay estimation in adder circuit using non-clocked pass gate families. In: 2006 International Conference on Electrical and Computer Engineering, 19-21 Dec. 2006, Dhaka, Bangladesh.

Senthilpari, C. and Diwakar, K. and Prabhu, C.M.R. and Singh, Ajay Kumar (2006) Power Deduction in Digital Signal Processing Circuit using Inventive CPL Subtractor Circuit. In: Conference.