Citation

Lee, Tiong Kiat (2003) VLSI Design Of A Bit Serial Arithmetic Logic Unit. Masters thesis, Multimedia University.

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Abstract

The arithmetic logic unit (ALU) is designed to perform bit serial operation on two 8 bits input. In this project , a Very High Speed Integrated Circuit Hardware Description Language (VHDL) code is written using the Altera MAX+Plus II environment to design, compile and simulate for each operation in the bit serial arithmetic logic unit. The details of each design steps from design entry, compilation, debugging, simulation and syntheis is described in this project.

Item Type:	Thesis (Masters)
Subjects:	T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics
Divisions:	Faculty of Engineering (FOE)
Depositing User:	Ms Rosnani Abd Wahab
Date Deposited:	15 Jul 2010 06:38
Last Modified:	15 Jul 2010 06:38
URII:	http://shdl.mmu.edu.my/id/eprint/966

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