Citation

Abdulrazzaq, Bilal I. and Ibrahim, Omar J. and Kawahito, Shoji and M. Sidek, Roslina and Shafie, Suhaidi and Md. Yunus, Nurul Amziah and Lee, Lini and Abdul Halin, Izhal (2016) Design of a Sub-Picosecond Jitter with Adjustable-Range CMOS Delay-Locked Loop for High-Speed and Low-Power Applications. Sensors, 16 (10). p. 1593. ISSN 1424-8220

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Abstract

A Delay-Locked Loop (DLL) with a modified charge pump circuit is proposed for generating high-resolution linear delay steps with sub-picosecond jitter performance and adjustable delay range. The small-signal model of the modified charge pump circuit is analyzed to bring forth the relationship between the DLL's internal control voltage and output time delay. Circuit post-layout simulation shows that a 0.97 ps delay step within a 69 ps delay range with 0.26 ps Root-Mean Square (RMS) jitter performance is achievable using a standard 0.13 µm Complementary Metal-Oxide Semiconductor (CMOS) process. The post-layout simulation results show that the power consumption of the proposed DLL architecture's circuit is 0.1 mW when the DLL is operated at 2 GHz.

Item Type:	Article
Uncontrolled Keywords:	Delay step, delay range, time jitter, Delay-Locked Loop (DLL), charge pump, Capacitor-Reset Circuit (CRC)
Subjects:	T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK452-454.4 Electric apparatus and materials. Electric circuits. Electric networks
Divisions:	Faculty of Engineering (FOE)
Depositing User:	Ms Suzilawati Abu Samah
Date Deposited:	22 May 2018 10:50
Last Modified:	22 May 2018 10:50
URII:	http://shdl.mmu.edu.my/id/eprint/6692

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