Citation

Thangasamy, Veeraiyah and Kamsani, Noor Ain and Hamidon, Mohd Nizar and Hashim, Shaiful Jahari and Yusoff, Zubaida and Bukhori, Muhammad Faiz (2015) Low power 18T pass transistor logic ripple carry adder. IEICE Electronics Express, 12 (6). ISSN 1349-2543

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Abstract

In this paper, a high-speed low-power 18T CMOS full adder design featuring full-swing output is proposed. The adder is designed and simulated using pass transistor logic of the 130 nm CMOS technology, at a supply voltage of 1.2 V. The obtained Power Delay Product (PDP) of its critical path is 22 × 10−18 J, which is a marked improvement of 61% to 98% compared against those of the 28T conventional CMOS, 20T transmission gate (TGA), 16T transmission function (TFA), 14T hybrid, 24T hybrid pass logic with static CMOS, and 28T differential pass logic (DPL) full adders simulated with the same process technology. Its power consumption is lower by 32% to 85%, with speed performance comparable to those of other high-speed adders reported in the literature. Occupying an aerial footprint of only 107 µm2 (8.00 µm × 13.41 µm), the proposed full adder is also capable to function at lower supply voltages of 0.4 V and 0.8 V without significant performance degradation.

Item Type:	Article
Subjects:	T Technology > TK Electrical engineering. Electronics Nuclear engineering T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics
Divisions:	Faculty of Engineering (FOE)
Depositing User:	Ms Nurul Iqtiani Ahmad
Date Deposited:	14 Apr 2015 02:56
Last Modified:	05 May 2015 02:08
URII:	http://shdl.mmu.edu.my/id/eprint/6179

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