Citation

Chinnaiyan, Senthilpari and Kumari Selvam, Rosalind Deena and Gajula Ramana, Murthy and Pitchandi, Velrajkumar and Diwakar, K. (2014) Low Power and 5.8 GHz Operating Frequency of Digital Frequency Divider Using Proposed Sequential Circuit. Australian Journal of Basic and Applied Sciences, 8 (1). pp. 273-281. ISSN 1991-8178

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Abstract

Background: The frequency divider is a critical element in ultra-high-speed applications of communication systems, which provides an important benchmark for the performance of high-speed technology. These frequency divider designs are based on CMOS technology and contain many newer gate configurations and device functions, which achieved in terms of high speed, low power dissipation and reduced chip size, which is a negative element that should be lowered at all costs to maintain high speed technological requirements. Objective: To design a 1/3 and 1/5 frequency divider circuit by using proposed JK flip-flop. To anaylse the power dissipation, maximum operating frequency and propagation delay. Results: Compared with conventional techniques, the proposed JK Flip-Flop based frequency divider circuit has a maximum operating frequency of 59.38GHz with 0.192 mW of power utilisation. Conclusion: the proposed design outperformed a comparable CMOS circuit in term of power dissipation, propagation delay, layout area and operating frequency. The circuit is designed using digital schematic CAD tools, while a layout editor is used for the layout generation. Layout versus simulation (LVS) is performed by a BSIM 4 analyser. This paper also presents the result of parametric analysis, including measured power dissipation and leakage current through the load capacitance and supply voltages that gives better performance than existing circuits.

Item Type:	Article
Uncontrolled Keywords:	Frequency Divider JK Flip-Flop,Low-Power, Propagation Delay, Parametric Analysis, Operating Frequency
Subjects:	T Technology > TA Engineering (General). Civil engineering (General)
Divisions:	Faculty of Engineering and Technology (FET)
Depositing User:	Ms Rosnani Abd Wahab
Date Deposited:	10 Nov 2016 03:07
Last Modified:	10 Nov 2016 03:07
URII:	http://shdl.mmu.edu.my/id/eprint/6068

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