Citation

Murthy, G. Ramana (2012) Design of low-power multiplexer-based adders for digital infinite impulse response filter. PhD thesis, Multimedia University.

Full text not available from this repository.

Abstract

Addition is a fundamental arithmetic operation used extensively in many Very Large Scale Integration (VLSI) systems, such as application-specific Digital Signal Processing (DSP) and microprocessor systems. This thesis presents a novel high-speed and high-performance multiplexer-based full adder cell (MUX-12T) for low-power applications. The proposed MUX-12T full adder is composed of two separate modules with identical hardware configurations to generate Sum and C signals in a parallel manner. The MUX-12T adder circuit is analysed in interconnect analysis using the Microwind 2 CAD tool to evaluate layout thickness, width and height. The MUX-12T adder is modelled for its RLC values by varying the adders width, height and length according to body alter bias conditions to identify the R, L and C parameters that suit low-power applications. The simulation results clearly display the superiority of the design in terms of power dissipation, propagation delay, layout area and Power-Delay Product (PDP). The RLC modelled results for R, L and C values imply that the design is suitable for low-power circuits. The MUX-12T adder circuit is compared with several recently published adders at various feature sizes to demonstrate its superiority. The MUX-12T adder consumes 0.482 µW of power, has a 127.3 ps propagation delay and occupies an area of 10x9.3 µm2 at a 90 nm feature size. In addition, a 1-bit full adder cell (MCIT-6T) that uses only six transistors is proposed in this thesis. In this design, three multiplexers and one inverter are used to minimise the transistor count and reduce power consumption. The proposed MCIT6T full adder clearly outperforms existing adders in its temperature sustainability behaviour versus power dissipation and its leakage current parameters. The low power and low transistor count qualify the MCIT-6T full adder cell for power efficient applications. The cell is designed using a combination of the Multiplexing Control Input Technique (MCIT) and Boolean identities. The design effectively adopts the MCIT technique to alleviate the threshold voltage-loss problem commonly encountered in Pass Transistor Logic (PTL)design.

Item Type:	Thesis (PhD)
Additional Information:	Call No.: TK7874.75 G73 2012
Subjects:	T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions:	Faculty of Engineering and Technology (FET)
Depositing User:	Ms Nurul Iqtiani Ahmad
Date Deposited:	20 May 2014 03:15
Last Modified:	20 May 2014 03:15
URII:	http://shdl.mmu.edu.my/id/eprint/5514

Downloads

Edit (login required)