Citation

Yeo, Joel Yee Kiat (2012) Optimal modeling fill guide for improved interconnect performance. Masters thesis, Multimedia University.

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Abstract

Chemical mechanical polishing (CMP) planarization process is an important step in fabrication for multi-layer metallization to create and design IC metallization and via interconnections. Fill synthesis methodologies are innovated by inserting dummy fill structures into the surrounding functional interconnects to help reduced metal and oxide topography variations which caused by post-CMP planarization effects. In transition to ultra-deep sub-micron (UDSM) design technology nodes, fill synthesis increasingly causing performances impact to the interconnect design due to the parasitic capacitances induced by the dummy fill structures. Meeting CMP density design rules alone are no longer sufficient. Large spacing setbacks between functional interconnects and dummy fill structures are commonly used to minimize parasitic capacitance, however as design scaled further into the nanometer regime, a huge percentage of metal densities are sacrificed and achieving minimum density requirements in certain areas are not possible. A fill synthesis solution is proposed in this thesis to optimize and balance both of the requirements in-between chip performances and yield requirements.

Item Type:	Thesis (Masters)
Additional Information:	Call No.: TK7874.84 Y46 2012
Subjects:	T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics
Divisions:	Faculty of Engineering (FOE)
Depositing User:	Ms Nurul Iqtiani Ahmad
Date Deposited:	27 Mar 2014 02:43
Last Modified:	27 Mar 2014 02:43
URII:	http://shdl.mmu.edu.my/id/eprint/5401

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