VLSI Design of a Wavelet Processing Core


Sze, Wei Lee and Soon, Chieh Lim (2006) VLSI Design of a Wavelet Processing Core. IEEE Transactions on Circuits and Systems for Video Technology, 16 (11). pp. 1350-1361. ISSN 1051-8215

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A processing core architecture for the implementation of the discrete wavelet transform (DWT), optimized for throughput, scalability and programmability is proposed. The architecture is based on the RISC architecture with an instruction set specifically designed to facilitate the implementation of wavelet-based applications and a memory controller optimized for the memory access pattern of DWT processing.

Item Type: Article
Subjects: T Technology > T Technology (General)
Q Science > QA Mathematics > QA71-90 Instruments and machines > QA75.5-76.95 Electronic computers. Computer science
Divisions: Faculty of Engineering and Technology (FET)
Depositing User: Ms Suzilawati Abu Samah
Date Deposited: 13 Oct 2011 06:12
Last Modified: 03 Mar 2014 04:51
URII: http://shdl.mmu.edu.my/id/eprint/3250


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