Low power ROM Employing Dynamic Threshold-Voltage MOSFET (DTMOS) Technique


M., Mustapa and F., Mohd-Yasin and M. K., Khaw and M. B. I., Reaz and A., Kordesch (2008) Low power ROM Employing Dynamic Threshold-Voltage MOSFET (DTMOS) Technique. In: IEEE International Conference on Semiconductor Electronics , 25-27 NOV 2008 , Johor Bahru, MALAYSIA.

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This paper examines the performance of two 128-bit ROM circuits, implemented on Silterra 0.18u CMOS process. The first circuit is built using standard NMOS transistors, runs on 0.9V supply voltage, has gate voltage of 0.45V and consumes 102.07 mu W power. The second circuit is designed partly using Dynamic Threshold-Voltage MOSFET (DTMOS) transistors with the aim to minimize power consumption. It runs on 0.7V supply and has gate voltage of 0.35V. The DTMOS approach is implemented on the 128-bit ROM core and in the pull up circuit of the column decoder. The latter ROM circuit's power consumption is 38.93 mu W, 61.86% less than the former, at the expenses of larger die area due to the usage of deep n-well process. The standard and DTMOST circuits have the die areas of 0.139 mu m2 and 0.235 mu m2, respectively.

Item Type: Conference or Workshop Item (Paper)
Subjects: T Technology > T Technology (General)
Q Science > QA Mathematics > QA71-90 Instruments and machines > QA75.5-76.95 Electronic computers. Computer science
Divisions: Faculty of Engineering and Technology (FET)
Depositing User: Ms Suzilawati Abu Samah
Date Deposited: 21 Sep 2011 06:52
Last Modified: 21 Sep 2011 06:52
URII: http://shdl.mmu.edu.my/id/eprint/2890


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