Citation

Lee, Chu Liang and Visvanathan, Tasigen and Chan, Kah Yoong and Senthilpari, Chinnaiyan (2026) Integration of Multiplication and Floating-Point Extensions in Risc-V: Design and Synthesis. Journal of Engineering Technology and Applied Physics, 8 (2). p. 58. ISSN 2682-8383

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Abstract

Thisproject involves the design and implementation of the multiplication (M) and floating point (F) extensions and their integrationwiththebase RV32I processor in formingan RV32IMF processor. The multiplication and division unit (MDU) and floating-point unit (FPU) aredesigned to support these extensions. The MDU is a single module that handles multiplication and division between combinations of signed and unsigned integers. The FPU design is hierarchical with several submodules, such as the AddSubFPU, MulFPU, and DivFPU modules. The single AddSubFPu module handles addition and subtraction. MulFPU and DivFPUhandle the multiplication and division, respectively. Additionally, FPU’s top-level module handles sign-injection instructions. FPU Arithmetic demonstrates high accuracy, with relative error limited to around 0.25%. Performance analysis shows an increase in area and power usage compared to the baseline design, along with improved critical path timing. The processor demonstrates stable operation at various frequencies, with one hundred megahertz offering a favourable balance of performance and efficiency.

Item Type:	Article
Uncontrolled Keywords:	Multiplication and division unit
Subjects:	T Technology > TA Engineering (General). Civil engineering (General)
Divisions:	Faculty of Artificial Intelligence & Engineering (FAIE)
Depositing User:	Ms Rosnani Abd Wahab
Date Deposited:	12 Oct 2026 02:05
Last Modified:	12 Oct 2026 02:05
URII:	http://shdl.mmu.edu.my/id/eprint/16893

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