Citation

Lam, Yan Qei and Pang, Wai Leong and Goh, Hui Hwang and Chandra, Balapanur Mouli and Prasanth, B Venkata and Chan, Kah Yoong (2025) A Nine-Level Switched-Capacitor Multilevel Inverter with Reduced Component Stress and Optimised Component Count. In: 9th International Conference on Recent Advances and Innovations in Engineering, ICRAIE 2025, 23 August 2025 - 24 August 2025, Kuala Lumpur.

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Abstract

Due to the advantages of Switched-Capacitor Multilevel Inverters (SC-MLIs), extensive research has been conducted to counter the limitations of conventional MLIs. However, many researched topologies faced difficulty in achieving a high boosting factor and low voltage stress with a low component count. Therefore, a nine-level SC-MLI topology was proposed to achieve a high boosting factor of four and an optimised component count, as well as reducing the voltage stress across the switches within the MLI. Eight switches, five diodes, three capacitors and a single DC source were used in the proposed topology. The topology was simulated and validated in MATLAB/Simulink. The topology reduced the Total Standing Voltage (TSV) of 4.5 p.u., and the voltage stress by 10% compared to the existing topologies. A modified Phase-Disposition Pulse Width Modulation (PD-PWM) scheme was implemented in the topology and achieved a Total Harmonic Distortion (THD) of 13.65% to the output voltage. The proposed topology is shown to be the lowest among all high-frequency PWM scheme-based nine-level SC-MLI topologies.

Item Type:	Conference or Workshop Item (Paper)
Uncontrolled Keywords:	Multilevel inverters
Subjects:	T Technology > T Technology (General)
Divisions:	Faculty of Artificial Intelligence & Engineering (FAIE)
Depositing User:	Ms Rosnani Abd Wahab
Date Deposited:	17 Mar 2026 02:25
Last Modified:	17 Mar 2026 02:27
URII:	http://shdl.mmu.edu.my/id/eprint/15462

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