Citation

Sridhar, Nagisetty (2024) Active Element-Based Class-J power amplifier design for wireless communication applications. PhD thesis, Multimedia University.

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Abstract

The evolution of wireless communication paves the path for 5G technology into the power sector, beyond mobile communication, particularly in smart grid communication applications that support large data transmission. For such applications, the deployment of 5G technology must reduce energy consumption and enhance bandwidth (BW) to improve wireless system operability. The power amplifier (PA) controls the energy consumption and BW, making it the most critical component in wireless communication systems. Among existing PAs, the class-J PA can provide a solution for efficiency and linearity trade-offs over wide BW. However, the existing class-J PA needs innovative designs to meet 5G wireless networks' conflicting requirements. This thesis presents a novel design approach of a class-J PA with an active inductor/element-based output matching network (OMN) for the smart grid’s sub-6 GHz 5G wireless networks. The proposed class-J PA is initially designed as a single-stage PA with a 5 GHz operating frequency using 130 nm CMOS technology in the MG EDA tool. As there is no provision for load pull simulations in the MG EDA tool, a single-stage class-J PA is designed and simulated with a 3.5 GHz operating frequency suitable for smart grid’s 5G wireless networks, to achieve the desired efficiency using the GaN transistor and load pull techniques in the ADS EDA tool. To improve the power gain, a two-stage class-J PA is designed and simulated at the same 3.5 GHz frequency in the ADS EDA tool. Key innovations in this design include the integration of an Active inductor (AI) to replace the passive lumped inductor in its OMN, to achieve tunability with reduced size. Among the proposed designs, the twostage class-J PA designed at 3.5 GHz achieves promising results, such as 53% PAE, 54% D.E, and 41dBm Pout with an improved power gain of 21dB across 400 MHz BW. The Pout at 3 dB compression point is 41 dBm while Psat is 41.4 dB demonstrating PA linearity. With the proposed double-ended active inductor (DEAI), the PA’s tunability and BW are validated and maintained as 400 MHz. Finally, the PA’s chip size is estimated as (12.5 × 31.8) μm2 through an active element-based layout design using the Silterra 130 nm CMOS technology in the MG EDA tool, revealing its feasibility for chip integration. These simulation results reveal that, compared to existing class-J mode PAs, the proposed two-stage class-J PA exhibit its suitability for emerging sub-6 GHz 5G wireless networks in smart Grid’s AMI applications.

Item Type:	Thesis (PhD)
Additional Information:	Call No.: TK7871.58.P6 N34 2024
Uncontrolled Keywords:	Power amplifiers
Subjects:	T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics > TK7871 Electronics--Materials
Divisions:	Faculty of Engineering (FOE)
Depositing User:	Ms Nurul Iqtiani Ahmad
Date Deposited:	04 Jul 2025 01:53
Last Modified:	04 Jul 2025 01:53
URII:	http://shdl.mmu.edu.my/id/eprint/14214

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