The Implementation of a Smart Sampling Scheme C2O Utilizing Virtual Metrology in Semiconductor Manufacturing


Tin, Tze Chiang and Tan, Saw Chin and Yong, Hing and Kim, Jimmy Ook Hyun and Teo, Eric Ken Yong and Wong, Joanne Ching Yee and Lee, Ching Kwang and Than, Peter and Tan, Angela Pei San and Phang, Siew Chee (2021) The Implementation of a Smart Sampling Scheme C2O Utilizing Virtual Metrology in Semiconductor Manufacturing. IEEE Access, 9. pp. 114255-114266. ISSN 2169-3536

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Virtual metrology (VM) is an enabling technology capable of performing virtual inspection on the metrology quality of wafers. Instead of physically acquiring the metrology measurements, VM applies conjecture models on the process data of wafers to estimate the measurements of the targeted metrology variables. Prior works on overlay VM system utilized fault detection and classification (FDC) data as the process data for the conjecture models. Hence, when FDC data are unavailable owing to FDC system enhancement works, FDC-based VM models would be rendered inefficacious. During such events, a competent VM system using a different modeling approach is required to sustain the production line until FDC data resumes availability and FDC-based VM reaches production state. Motivated by a real-world production environment of a 200mm semiconductor manufacturing plant (fab), a novel wafer lot-level modeling approach for overlay VM was proposed in our prior work. Using the proposed modeling, a smart sampling scheme was also designed in the same work. The smart sampling scheme consists of two conjecture tasks, with the first task classifies the overlay quality of the wafers, and the second task estimates the overlay errors of the wafers classified with normal overlay quality. The abnormal ones are diverted to the physical metrology station. In this paper, the implementation of a smart sampling system, C2O, using the designed scheme and its experimental results are presented. The experimental results showed that C2O is capable to achieve a true positive rate (TPR) of 71.34% for the classification task and mean absolute scaled error (MASE) of 9.59 for the regression task. The obtained results set the baseline to measure the efficacy of future enhancement works, which have been enlisted and underway to augment the performance of the system so that its competency meets the requirements of real fab.

Item Type: Article
Uncontrolled Keywords: Semiconductors, Metrology, Semiconductor device modeling, Task analysis
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics > TK7871 Electronics--Materials
Divisions: Faculty of Computing and Informatics (FCI)
Depositing User: Ms Nurul Iqtiani Ahmad
Date Deposited: 03 Oct 2021 15:05
Last Modified: 03 Oct 2021 15:05


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