RISC Design: Synthesis Of The MIPS Processor Core

Yew, Teong Guan (2003) RISC Design: Synthesis Of The MIPS Processor Core. Masters thesis, Multimedia University.

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Abstract

The idea of this project was to create a microprocessor as a building block in VHDL that later easily can be included in a larger design. MIPS (Microprocessor without Interlocked Pipeline Stages) is an example of a modern RISC (Reduced Instruction Set Computer) had been chosen for this project based on the simplicity of its instruction set and better performance then CISC.

Item Type: Thesis (Masters)
Subjects: Q Science > QA Mathematics > QA75.5-76.95 Electronic computers. Computer science > QA76.75-76.765 Computer software
Divisions: Faculty of Engineering (FOE)
Depositing User: Ms Rosnani Abd Wahab
Date Deposited: 13 Jul 2010 03:03
Last Modified: 13 Jul 2010 03:03
URI: http://shdl.mmu.edu.my/id/eprint/951

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