Design Of A 16- Bit adder Decoder Application Circuit


Lee, Lini and Chinnaiyan, Senthilpari and Selvam, Rosalind Deena Kumari (2019) Design Of A 16- Bit adder Decoder Application Circuit. Journal of Engineering Science and Technology., 14. pp. 249-260. ISSN 1823-4690

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The aim of this paper is the design of an adder which relates to error checking and updating circuits required for the analysis of decoder circuits. The parameters such as Delay, Power dissipation, and PDP are usually considered in the design process. The proposed adder circuit uses dynamic logic technique and designed with pass transistor logic TTL configuration. The reduction of components is achieved as two transistors for every logic cell using the dynamic logic design. The proposed adder is implemented in 16 bit by cascading the adder circuit using the carry select adder technique and considering the parameters of delay, power dissipation, and throughput. The generated layout was simulated using VLSI CAD tools for 70 nm and 180 nm feature sizes. The proposed circuit results reflected the intention of having a lower power dissipation of 7.5 nW, reduced delay of 0.127 ns and a throughput of 3.69×109 Gbps. This study emphasised that the proposed design resulted in a better output.

Item Type: Article
Uncontrolled Keywords: Decoder, Delay, Dynamic logic, LDPC, Power dissipation, Throughput.
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics
Divisions: Faculty of Engineering (FOE)
Depositing User: Ms Suzilawati Abu Samah
Date Deposited: 09 Mar 2022 03:01
Last Modified: 09 Mar 2022 03:01


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