Reliable data aware sram cell using FinFET technology


Prabhu, Chinnaraj Munirathina and Singh, Ajay Kumar and TG, Sargunam (2019) Reliable data aware sram cell using FinFET technology. ARPN Journal of Engineering and Applied Sciences, 14 (8). pp. 1574-1577. ISSN 1819-6608

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The low power and high performance Static Random Access Memory (SRAM) is the main constraint in modern VLSI systems. The SRAM cell power dissipation can be controlled to improve the system power, performance and reliability at a significant level. This research proposes a new technique of Reliable Data Aware (RDA) SRAM cell design using 14 nm FinFET technology to minimize the power dissipation, access delay for read and write operations and maximize the read stability. The proposed FinFET based SRAM design has been employed in RDA SRAM cell and the results analysis proved that the write power dissipation has reduced to 90.14% and read power is about 49.94% than the 6T cell. The read access time and stability of the suggested RDA cell have been improved.

Item Type: Article
Uncontrolled Keywords: FinFET, SRAM cell, power, performance, leakage current, stability.
Subjects: T Technology > TA Engineering (General). Civil engineering (General)
Divisions: Faculty of Engineering and Technology (FET)
Depositing User: Ms Suzilawati Abu Samah
Date Deposited: 15 Feb 2022 02:17
Last Modified: 15 Feb 2022 02:17


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