Architecture And Logic Design Of A Discrete Wavelet Transform Processor

Lim , Soon Chieh (2005) Architecture And Logic Design Of A Discrete Wavelet Transform Processor. Masters thesis, Multimedia University.

Full text not available from this repository.
Official URL: http://myto.perpun.net.my/metoalogin/logina.php

Abstract

Since the advent of wavelets in the 1980s, wavelet analysis has been applied to many different applications, such as video and image compression, digital communications, biomedical signal processing, medical imaging, matrix computation, digital signal processing, and video-conferencing. In this thesis, we propose a dedicated VLSI architecture for implementing the discrete wavelet transform (DWT). In this architecture, a wavelet processor based on a generic reduced-instruction-set-computing (RISC) architecture is designed and optimised for the DWT.

Item Type: Thesis (Masters)
Subjects: Q Science > QA Mathematics
Divisions: Faculty of Engineering (FOE)
Depositing User: Ms Rosnani Abd Wahab
Date Deposited: 02 Jul 2010 04:24
Last Modified: 02 Jul 2010 04:24
URI: http://shdl.mmu.edu.my/id/eprint/786

Actions (login required)

View Item View Item