Citation

Subramaniam, Shahmini and Singh, Ajay Kumar and Murthy, Gajula Ramana (2018) Design of power efficient stable 1-bit full adder circuit. IEICE Electronics Express, 15 (14). p. 20180552. ISSN 1349-2543

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Abstract

This paper presents design of 14-T 1-bit full adder power efficient Pass Transistor Logic (PTL) based stable circuit. Due to compact architecture, power consumption is low and response is faster. MC (Monte Carlo) shows that the circuit is more reliable against any statistical variations

Item Type:	Article
Uncontrolled Keywords:	MC (Monte Carlo) simulation,power efficient, pass transistor logic (PTL), 1-bit full adder circuit, reliability
Subjects:	T Technology > TA Engineering (General). Civil engineering (General) > TA349-359 Mechanics of engineering. Applied mechanics
Divisions:	Faculty of Engineering and Technology (FET)
Depositing User:	Ms Rosnani Abd Wahab
Date Deposited:	23 Mar 2021 22:29
Last Modified:	23 Mar 2021 22:29
URII:	http://shdl.mmu.edu.my/id/eprint/7527

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