Improved speed low power and low voltage SRAM design for LDPC application circuits


Senthilpari, Chinnaiyan and Kumari Selvam, Rosalind Deena and Lee, Lini (2018) Improved speed low power and low voltage SRAM design for LDPC application circuits. Journal of Engineering Science and Technology., 13 (3). pp. 822-837. ISSN 1823-4690

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The design of SRAM has evolved to suffice the need of the industry in terms of speed, power dissipation and other parameters. This paper proposed a SRAM design and an attempt has been made to design circuits using dynamic logic and pass transistor logic to obtain better performance in terms of speed, power dissipation and throughput. The dynamic logic would maintain voltage degradation by using the PMOS and NMOS transistor just as the CMOS logic, even though the design cell uses majority NMOS transistors. The proposed circuits are simulated using BSIM for different CMOS feature sizes of 70 nm, 90 nm, 120 nm and 180 nm. The results obtained have been analysed and shows that the proposed circuit of 8T performs much better as compared to other circuit configurations. There is significant improvement in power dissipation by 99.64 %, delay by 99.9 %, throughput of 490 Mbps and power delay product of 99.96 %.

Item Type: Article
Uncontrolled Keywords: Static random access memory, Improved speed, Dynamic logic, SRAM, LDPC, Throughput, Power dissipation.
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics > TK7885-7895 Computer engineering. Computer hardware > TK7895.M4 Memory systems
Divisions: Faculty of Computing and Informatics (FCI)
Depositing User: Ms Rosnani Abd Wahab
Date Deposited: 11 Nov 2020 11:43
Last Modified: 11 Nov 2020 11:43


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