Low Power and Improved Speed 1T DRAM Using Dynamic Logic


Senthilpari, Chinnaiyan and Pandiyan, S. K. and Nirmalraj, T. (2018) Low Power and Improved Speed 1T DRAM Using Dynamic Logic. Journal of Engineering Science and Technology., 13 (6). pp. 1636-1650. ISSN 1823-4690

[img] Text
Restricted to Repository staff only

Download (552kB)


The new trend of the DRAM design is to characterize by its reliability, delay, low power dissipation, and area. This paper dealt with the design of 1-bit DRAM and efficient implementation of a sense amplifier. The proposed 1-bit DRAM designed using dynamic logic design. The proposed circuit consists of buffers, 1 transistor, and capacitor. The circuit is schematized by DSCH2 and layout designs are generated by Microwind CAD tool. The designed and proposed circuits are considered bypass logic and Boolean reduction technique that reduced number of transistors per designed cell logic. The circuits are simulated in various feature sizes namely CMOS 70 nm, CMOS 90 nm, CMOS 120nm and corresponding voltages 0.7 V, 1 V, 1.2 V respectively. Our proposed dynamic logic DRAM circuit has compared with the designed circuit and other existing circuits. Our proposed and designed circuit gives better results in terms of power dissipation, speed, and Area. (R-2) The projected 1-bit DRAM has an outcome and achieved low power 0.229 µW, the area of 22×13µm, the propagation delay of 21 ps and a speed of 0.17 GHz.

Item Type: Article
Uncontrolled Keywords: Dynamic random access memory, DRAM, Dynamic logic, Low power and speed, Propagation delay
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics > TK7885-7895 Computer engineering. Computer hardware
Divisions: Faculty of Engineering (FOE)
Depositing User: Ms Rosnani Abd Wahab
Date Deposited: 25 Oct 2020 21:46
Last Modified: 25 Oct 2020 21:46
URII: http://shdl.mmu.edu.my/id/eprint/7231


Downloads per month over past year

View ItemEdit (login required)