Layout parameter analysis in Shannon expansion theorem based on 32 bit adder circuit


Senthilpari, Chinnaiyan and Diwakar, K. and Munusamy, Kumar and Francisca, J. Sheela (2017) Layout parameter analysis in Shannon expansion theorem based on 32 bit adder circuit. Engineering Science and Technology, an International Journal, 20 (1). pp. 35-40. ISSN 2215-0986

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The 1-bit adder circuits are schematized using pass transistor logic (PTL) technique, that’s optimized by the Shannon expansion theorem. The proposed 32 bit carry increment adder (CIA) circuit is designed by bit slice method. The CIA adder layout gives tremendous change compared to existing author results. The proposed circuit achieved better performance on power consumption, speed, throughput, and area. The 32-bit adder circuits are implemented in various types of 1-bit adder cells, such as Shannon, Mixed- Shannon and MCIT-7T. Furthermore, the 32-bit CIA adder layout is furtherly investigated for RLC inter- connect parameter such as capacitive impedance, inductive impedance, power factor sin / , tan / for applying frequency. The 32 bit adder circuit acts in a better way than existing circuits in terms of power dissipation, delay, throughput, latency, power factor, sin / and tan / . Ó 2016 Karabuk University. Publishing services by Elsevier B.V. This is an open access article under the CC BY-NC-ND license

Item Type: Article
Uncontrolled Keywords: RLC modelling, 32 bit adder, Shannon theorem, Interconnect parameter, Power factor
Subjects: T Technology > TA Engineering (General). Civil engineering (General)
Divisions: Faculty of Engineering (FOE)
Depositing User: Ms Rosnani Abd Wahab
Date Deposited: 06 Aug 2020 03:27
Last Modified: 06 Aug 2020 03:29


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