Design of Power Efficient 32-kilobit Memory Compiler for Variability Tolerance


Saadatzi, Mohammadsadegh (2015) Design of Power Efficient 32-kilobit Memory Compiler for Variability Tolerance. Masters thesis, Multimedia University.

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The thesis presents a data-dependent write assist (DDWS) dynamic SRAM cell to reduce the power consumption and enhance the variability tolerance against process, voltage, temperature (PVT) and aging effect. The cell performs write operation using separate write signal WS instead of wordline WL to reduce the discharging activity at the write bitline in order to save the dynamic power and enhance the write ability. Due to stack effect, the read leakage current is reduced during write operation. The lower voltage drops on respective bitline, lower leakage current and lower parasitic capacitance results 60.4% lower write power and 52.8% lower read power compared to the other cells. The storage node does not float during read operation and thus cell is not sensitive to any positive noise. The data in the cell is maintained even power supply is reduced to 300mV. As process variation becoming growing concern in deep sub-micron devices, it is necessary to study the operation of the ratioed structure under process variations and device mismatch. The global and local variations can cause the traditional ratioed logic to lose functionality. The proposed cell has been investigated under process, temperature and voltage (PVT) variations during read/write operations and hold mode which shows higher immunity towards the PVT variation.

Item Type: Thesis (Masters)
Additional Information: Call No.: TK7895.M4 S23 2015
Uncontrolled Keywords: Random access memory
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics
Divisions: Faculty of Engineering and Technology (FET)
Depositing User: Ms Nurul Iqtiani Ahmad
Date Deposited: 07 Sep 2017 10:49
Last Modified: 07 Sep 2017 10:49


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