Citation

Gajula Ramana, Murthy and Chinnaiyan, Senthilpari and Pitchandi, Velrajkumar and Tien Sze, Lim (2014) Monte-Carlo analysis of a new 6-T full-adder cell for power and propagation delay optimizations in 180 nm process. Engineering Computations, 31 (2). pp. 149-159. ISSN 0264-4401

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Abstract

Demand and popularity of portable electronic devices are driving the designers to strive for higher speeds, long battery life and more reliable designs. Recently, an overwhelming interest has been seen in the problems of designing digital systems with low power at no performance penalty. Most of the very large-scale integration applications, such as digital signal processing, image processing, video processing and microprocessors, extensively use arithmetic operations. Binary addition is considered as the most crucial part of the arithmetic unit because all other arithmetic operations usually involve addition. Building low-power and high-performance adder cells are of great interest these days, and any modifications made to the full adder would affect the system as a whole. The full adder design has attracted many designer's attention in recent years, and its power reduction is one of the important apprehensions of the designers. This paper presents a 1-bit full adder by using as few as six transistors (6-Ts) per bit in its design. The paper aims to discuss these issues.

Item Type:	Article
Uncontrolled Keywords:	Full-adder, Low-power, High-speed, Monte-Carlo analysis, Multiplexing, Pass transistor logic
Subjects:	T Technology > TA Engineering (General). Civil engineering (General)
Divisions:	Faculty of Engineering and Technology (FET)
Depositing User:	Ms Rosnani Abd Wahab
Date Deposited:	10 Nov 2016 02:55
Last Modified:	10 Nov 2016 02:55
URII:	http://shdl.mmu.edu.my/id/eprint/6067

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