Low-power reliable SRAM cell for write/read operation

Prabhu, Chinnaraj Munirathina and Singh, Ajay Kumar (2015) Low-power reliable SRAM cell for write/read operation. IEICE Electronics Express, 11 (21). pp. 1-6. ISSN 1349-2543

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Abstract

Low power SRAM cell is a critical component in modern VLSI systems. The major portion of the power dissipation in the SRAM cell is due to large voltage swing on the bit lines during write operation. In this paper, a low-power reliable (LPR) SRAM cell is proposed for minimizing the power consumption and to enhance the performance. A new write mechanism is proposed to reduce the charging/discharging activity on the respective bit lines. The cell is simulated in terms of power, delay and static noise margin (SNM). The simulated results show that write and read power of the proposed LPR cell are reduced up to 78% and 50% at 0.7 V (in 65 nm technology) respectively compared to the 6T cell. The proposed design achieves 2.4× higher read static noise margin (SNM) than the 6T cell.

Item Type: Article
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions: Faculty of Engineering and Technology (FET)
Depositing User: Ms Nurul Iqtiani Ahmad
Date Deposited: 22 Dec 2014 09:19
Last Modified: 22 Dec 2014 09:19
URI: http://shdl.mmu.edu.my/id/eprint/5868

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