An ultra-low power and area efficient 10 bit digital to analog converter architecture

Lee, Lini and Shahruddin, Iffa (2014) An ultra-low power and area efficient 10 bit digital to analog converter architecture. In: 2014 IEEE International Conference on Semiconductor Electronics (ICSE). IEEE, pp. 305-308. ISBN 978-1-4799-5760-6

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Abstract

An ultra-low power and area efficient successive approximation register (SAR) analog-to-digital converter (ADC) is presented. To achieve ultra-low power performance, a digital-to-analog converter (DAC) architecture is proposed that combined a 4-bit thermometer coded and a 6-bit C-2C array to form a 10-bit DAC. Thereby, power consumption and area of the design are drastically reduced by virtue of lower switching activity and smaller size capacitor array. Add on to that, the architecture also has better linearity. The proposed 10-bit DAC is designed and simulated in a 0.18 μm CMOS process. Simulation results show that it only consumed 1.74 nW at 1.5 V power supply.

Item Type: Book Section
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions: Faculty of Engineering (FOE)
Depositing User: Ms Nurul Iqtiani Ahmad
Date Deposited: 18 Nov 2014 05:32
Last Modified: 18 Nov 2014 05:32
URI: http://shdl.mmu.edu.my/id/eprint/5821

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