Low power and low voltage SRAM design for LDPC codes hardware applications

Kumari Selvam, Rosalind Deena and Senthilpari, Chinnaiyan and Lee, Lini (2014) Low power and low voltage SRAM design for LDPC codes hardware applications. In: 2014 IEEE International Conference on Semiconductor Electronics (ICSE). IEEE, pp. 332-335. ISBN 978-1-4799-5760-6

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Abstract

The Low Voltage Low Power (LVLP) 8T, 11T, 13T and ZA SRAM cell is designed using the dynamic logic SRAM cell. The SRAM cells are implemented using pass transistor logic technique, which is mainly focused on read and write operation. The circuits are designed by using DSCH2 circuit editor and their layouts are generated by MICROWIND3 layout editor. The Layout Versus Simulation (LVS) design has been verified using BSIM 4 with 65nm technology and with a corresponding voltage of 0.7V respectively. The simulated SRAM layouts are verified and analyzed. The SRAM 8T gives power dissipation of 0.145 microwatts, propagation delay of 37.2 pico seconds, area of 14 × 8 micrometers and a throughput of 4.037 nano seconds.

Item Type: Book Section
Subjects: Q Science > QA Mathematics > QA75.5-76.95 Electronic computers. Computer science
T Technology > TA Engineering (General). Civil engineering (General)
Divisions: Faculty of Computing and Informatics (FCI)
Faculty of Engineering (FOE)
Depositing User: Ms Nurul Iqtiani Ahmad
Date Deposited: 18 Nov 2014 05:19
Last Modified: 18 Nov 2014 05:19
URI: http://shdl.mmu.edu.my/id/eprint/5819

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