New fault isolation method during functional test in manufacturing

Lee, Lini and Phuah, Yee Fei (2012) New fault isolation method during functional test in manufacturing. Advanced Materials Research, 479-48. pp. 2572-2576. ISSN 1662-8985

Full text not available from this repository.
Official URL: http://dx.doi.org/10.4028/www.scientific.net/AMR.4...

Abstract

Stop Clock Design-for-Testability (DFT) and Scan Dump DFT are integrated and implemented to trap the digital logic inside combinational and sequential logics for fault isolation (FI) purpose. Both DFTs enable functional test result to be dumped out structurally during functional test at manufacturing. Validation is performed on RTL simulation using test pattern and it is shown that the real silicon data matched the simulation results. Hence a new FI method has been established on the fly, capable in manufacturing.

Item Type: Article
Subjects: T Technology > TA Engineering (General). Civil engineering (General)
Divisions: Faculty of Engineering (FOE)
Depositing User: Ms Rosnani Abd Wahab
Date Deposited: 27 Jan 2014 03:12
Last Modified: 10 Jul 2014 02:18
URI: http://shdl.mmu.edu.my/id/eprint/5001

Actions (login required)

View Item View Item