Performance Analysis of Reversed Binary Decision Diagram Pass Transistor Logic Synthesis

Bhuvaneswari, Thangavel and Prasad, Vishnuvajjula and Singh, Ajay Kumar and Senthilpari, Chinnaiyan (2011) Performance Analysis of Reversed Binary Decision Diagram Pass Transistor Logic Synthesis. International Journal of Circuit Theory and Applications, 41 (8). pp. 844-853. ISSN 00989886

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Official URL: http://dx.doi.org/10.1002/cta.822

Abstract

Binary decision diagrams (BDDs) are the most frequently used data structure for the representation and handling of Boolean functions because of their excellent time and space efficiencies. In this article, a reversed BDD-based pass transistor logic (PTL) logic synthesis is presented for low-power and high-performance circuits without exploiting the canonical property of BDDs. The procedure of the reversed BDD transformation into PTL is achieved by a one-to-one correspondence with the BDD node and PTL cell. Layouts are generated for the benchmark circuits and simulated in terms of power dissipation, propagation delay and area. The reversed BDD technique performs better in terms of area, delay and power dissipation due to the regularity, a reduced critical path, less interconnection wires, a multiplexer-based construction of PTL circuits, and less switching activities. Copyright (c) 2011 John Wiley & Sons, Ltd.

Item Type: Article
Subjects: T Technology > T Technology (General)
T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics
Divisions: Faculty of Engineering and Technology (FET)
Depositing User: Ms Suzilawati Abu Samah
Date Deposited: 28 Aug 2013 01:47
Last Modified: 28 Aug 2013 01:47
URI: http://shdl.mmu.edu.my/id/eprint/3906

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