Self-reduction quiescent current low power low dropout regulator for SoC application

Liang, L.C. and Sidek, R.M. (2012) Self-reduction quiescent current low power low dropout regulator for SoC application. Advanced Materials Research, 591-593. pp. 2632-2635. ISSN 10226680

Full text not available from this repository.

Abstract

A low power low-dropout (LDO) voltage regulator with self-reduction quiescent current is proposed in this paper. This proposed capacitorless LDO for Silicon-on-Chip (SoC) application has introduced a self-adjustable low-impedance circuitry at the output of LDO to attain stability critically during low output load current (less than a few hundred of micro-ampere). When the LDO load current increases, it reduces the LDO output impedance and moved the pole towards higher frequency away from the dominant pole and improving the system stability. When this happen, less amount of quiescent current is needed for the low-impedance circuitry to sustain the low output impedance. In this proposed LDO, the quiescent current that been used to sustain the low output impedance will be self-reduced when the output load current increases. Thus, the reduction of quiescent current at low output load current has tremendously improved the efficiency. The simulation results have shown a promising stability at low load current 0~1mA. The dropout voltage for this LDO is only 100mV at 1.2V supply. The proposed LDO is validated using Silterra 0.13_m CMOS process model and designed with high efficiency at low output load current.

Item Type: Article
Subjects: T Technology > TA Engineering (General). Civil engineering (General)
Divisions: Faculty of Engineering (FOE)
Depositing User: Users 1102 not found.
Date Deposited: 31 Dec 2012 00:38
Last Modified: 31 Dec 2012 00:38
URI: http://shdl.mmu.edu.my/id/eprint/3747

Actions (login required)

View Item View Item