Citation

Khalek, Faizal and Sulaiman, Mohd-Shahiman and Yusoff, Zubaida (2007) An 8-Gb/s half-rate clock and data recovery circuit. In: IEEE International Conference on Electron Devices and Solid-State Circuits, 20-22 DEC 2007 , Tainan, TAIWAN.

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Abstract

This paper presents circuit design and simulation result of the 8-Gb/s half-rate clock and data recovery circuit (CDR) by 0.18u process technology. The linear phase detector was used for the CDR and able to give linear relation of the phase error between 35ps to 110ps. While the data output jitter p-p is 4.6ps and the clock jitter p-p is 6.6ps. The power consumption is 55mW from a 1.8V voltage supply.

Item Type:	Conference or Workshop Item (Paper)
Subjects:	T Technology > T Technology (General) Q Science > QA Mathematics > QA71-90 Instruments and machines > QA75.5-76.95 Electronic computers. Computer science
Divisions:	Faculty of Engineering and Technology (FET)
Depositing User:	Ms Suzilawati Abu Samah
Date Deposited:	18 Oct 2011 06:39
Last Modified:	18 Oct 2011 06:39
URII:	http://shdl.mmu.edu.my/id/eprint/3153

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