A fast-lock delay-locked loop architecture with improved precharged PFD

Lip-Kai, Soh and Sulaiman, Mohd-Shahiman and Yusoff, Zubaida (2008) A fast-lock delay-locked loop architecture with improved precharged PFD. Analog Integrated Circuits and Signal Processing, 55 (2). pp. 149-154. ISSN 0925-1030

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Official URL: http://dx.doi.org/10.1007/s10470-008-9131-7

Abstract

In this paper, a dual charge pump architecture for fast-lock delay-locked loop (DLL) is proposed and analyzed. The proposed fast lock DLL uses only one phase frequency detector (PFD) to perform dual path tuning and a lock control circuit to control the switching between the two path. An improved PFD is proposed to reduce the output jitter by reducing the one-shot pulse produced when the reference signal and feedback signal is in phase. The proposed DLL circuit is designed based on the Silterra 0.18-mu m 1P6M CMOS process with a 1.8-V supply voltage. The active area of the proposed DLL circuit is 327.46 x 116.16 mu m. An experimental chip was implemented and measured. The measurement results show that the proposed DLL has fast locking properties.

Item Type: Article
Subjects: T Technology > T Technology (General)
Q Science > QA Mathematics > QA75.5-76.95 Electronic computers. Computer science
Divisions: Faculty of Engineering and Technology (FET)
Depositing User: Ms Suzilawati Abu Samah
Date Deposited: 12 Sep 2011 02:08
Last Modified: 13 Feb 2014 07:44
URI: http://shdl.mmu.edu.my/id/eprint/2738

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