A 5Gbit/s CMOS clock and data recovery circuit


Sulaiman , Mohd Shahiman and Mohd-Yasin,, F and Reaz,, Mamun B. I. and Soon-Hwei,, Tan and Kok-Siang,, Tan (2005) A 5Gbit/s CMOS clock and data recovery circuit. 2005 IEEE CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, PROCEEDINGS. pp. 415-418.

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This paper presents a half-rate 5Gb/s clock and data recovery circuit. Retiming of data is done by the linear PD that provides practically no systematic offset for the frequency band of interest The circuit was designed in a 0.18-mu m CMOS process and occupies an active area of 0.2 x 0.32 mm(2). The CDR exhibits an RMS jitter of +/- 1.2 ps and a peak-to-peak jitter of 5ps. The power dissipation is 97mW from a 1.8-V supply.

Item Type: Article
Subjects: T Technology > TA Engineering (General). Civil engineering (General)
Depositing User: Ms Rosnani Abd Wahab
Date Deposited: 22 Aug 2011 03:01
Last Modified: 22 Aug 2011 03:01
URII: http://shdl.mmu.edu.my/id/eprint/2407


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