A 160-mhz 45-mW asynchronous dual-port 1-mb CMOS SRAM


Soon-Hwei, , Tan and Sulaiman, , Mohd S. and Poh-Yee, , Loh (2005) A 160-mhz 45-mW asynchronous dual-port 1-mb CMOS SRAM. 2005 IEEE CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, PROCEEDINGS. pp. 351-354.

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A 160-Mhz 45-mW asynchronous dual-port 1-Mb CMOS SRAM is described. A minimum read access time of 4.26ns is achieved, with an active power figure of 31 mW, data retention capability at 0.1 V VDD across all skews with varied temperature, and yet consume a standby power of only 80nW. Simulation results show that the circuit functions properly over a wide range of Process, Voltage & Temperature (PVT) corners. SRAM was custom designed using TSMC CMOS 0.25 mu m 1P5M Salicide process with a total die size of approximately 115mm(2).

Item Type: Article
Subjects: T Technology > TA Engineering (General). Civil engineering (General)
Divisions: Faculty of Engineering (FOE)
Depositing User: Ms Rosnani Abd Wahab
Date Deposited: 22 Aug 2011 03:02
Last Modified: 22 Aug 2011 03:02
URII: http://shdl.mmu.edu.my/id/eprint/2406


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