A low-power high-speed 1-mb CMOS SRAM


Tan, , SH and Loh, , PY and Sulaiman, , MS (2006) A low-power high-speed 1-mb CMOS SRAM. DELTA 2006: THIRD IEEE INTERNATIONAL WORKSHOP ON ELECTRONIC DESIGN, TEST AND APPLICATIONS. pp. 281-286.

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An asynchronous dual-port 1-Mb CMOS SRAM is described. The SRAM can operate at a maximum frequency of 220MHz in dual-port mode and dissipates a minimum active power of 31mW and consumes a minimum standby power of 80nW. Simulation results show that the circuit functions properly over a wide range of Process, Voltage & Temperature (PVT) corners. SRAM was custom designed using TSMC CMOS 0.25 mu m 1P5M Salicide process and occupies a Silicon area of approximately 115mm(2) (11.5mm x 10mm).

Item Type: Article
Subjects: T Technology > TA Engineering (General). Civil engineering (General)
Divisions: Faculty of Engineering (FOE)
Depositing User: Ms Rosnani Abd Wahab
Date Deposited: 23 Sep 2011 02:42
Last Modified: 23 Sep 2011 02:42
URII: http://shdl.mmu.edu.my/id/eprint/2081


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