Power Deduction in Digital Signal Processing Circuit using Inventive CPL Subtractor Circuit

Senthilpari, C. and Diwakar, K. and Prabhu, C.M.R. and Singh, Ajay Kumar (2006) Power Deduction in Digital Signal Processing Circuit using Inventive CPL Subtractor Circuit. In: Conference.

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Official URL: http://dx.doi.org/10.1109/SMELEC.2006.380751

Abstract

The proposed 4 bit subtractor circuit is designed by using bit slice method of complementary pass transistor logic (CPL), which is suitable for applications like fast shifting; multiplier/adder in the loop cycle of DSP data processing device. The circuit can perform real time computational tasks at high speed. The designed circuit is performing efficiently in filtering signal at 100-520MHz sampling rate in real time. We have analyzed the proposed circuit for submicron regime, whose layout is designed by using microwind III VLSI CAD tools, in terms of propagation delay, power consumption, power dissipation and area. In 50nm analysis, the proposed circuit is found to dissipate less power (similar to 0.46 mu W) and possess less overall area of order of 423 mu m(2). The propagation delay is 9.5206x10(-12) sec. In DSP architecture, time and area are the critical components which are responsible for the efficient execution of arithmetic and logical operation. Our proposed circuit is enhancing, complete set of instruction cycle, passing at speed of 9.0 GHz, which is higher than reported results.

Item Type: Conference or Workshop Item (Paper)
Subjects: T Technology > TA Engineering (General). Civil engineering (General)
Divisions: Faculty of Information Science and Technology (FIST)
Depositing User: Ms Rosnani Abd Wahab
Date Deposited: 10 Aug 2011 06:36
Last Modified: 10 Aug 2011 06:36
URI: http://shdl.mmu.edu.my/id/eprint/2055

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