A methodology for optimum delay, skew, and power performances in an FPGA clock network

Sulaiman, Mohd S. (2006) A methodology for optimum delay, skew, and power performances in an FPGA clock network. INFORMACIJE MIDEM-JOURNAL OF MICROELECTRONICS ELECTRONIC COMPONENTS AND MATERIALS, 36 (2). pp. 85-90. ISSN 0352-9045

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Abstract

A methodology for FPGA clock network optimisation is presented. The algorithms for optimisation of clock skew, delay, and power considering slew rate constraint for an FPGA fixed-clock network are implemented and verified on SX 32 FPGA chip. Measurements indicated a 60% reduction in clock slew rate and a 22% improvement in power dissipation when compared to the results of the initial, un-optimised chip.

Item Type: Article
Subjects: T Technology > TA Engineering (General). Civil engineering (General)
Divisions: Faculty of Engineering (FOE)
Depositing User: Ms Rosnani Abd Wahab
Date Deposited: 23 Sep 2011 03:21
Last Modified: 23 Sep 2011 03:21
URI: http://shdl.mmu.edu.my/id/eprint/1966

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