A 1.3-Gsample/s interpolation with flash CMOS ADC based on active interpolation technique

Seemi, S. and Sulaiman, Mohd. S. and Farooqui, A. S. (2006) A 1.3-Gsample/s interpolation with flash CMOS ADC based on active interpolation technique. Analog Integrated Circuits and Signal Processing, 47 (3). pp. 273-280. ISSN 0925-1030

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Official URL: http://dx.doi.org/10.1007/s10470-006-5369-0

Abstract

In this paper, the design of a high-speed low-voltage CMOS interpolation with flash analog-to-digital converter (ADC) in CMOS 0.18-mu m process is presented. The use of summing differential amplifiers operating in continuous time for interpolation and resistor averaging circuit have significantly improved the circuit's linearity. The new interpolation technique has improved the pertinent phase delay problem of voltage interpolation enormously. A technique to reduce metastability errors in the Error Correction Circuitry is also presented. The circuit achieves a maximum sampling speed of 1.3 GHz. The measured signal-to-noise-plus-distortion ration (SNDR) is 32 dB at 500 MHz. Peak DNL and INL are less than 0.15 LSB and 0.35 LSB, respectively. This ADC consumes about 600 mW from 1.8 V at full speed. The chip occupies 0.56-mm(2) stop active area, prototyped in CMOS 0.18-mu m technology.

Item Type: Article
Subjects: Q Science > QA Mathematics > QA75.5-76.95 Electronic computers. Computer science
Divisions: Faculty of Engineering (FOE)
Depositing User: Ms Rosnani Abd Wahab
Date Deposited: 23 Sep 2011 03:27
Last Modified: 23 Sep 2011 03:27
URI: http://shdl.mmu.edu.my/id/eprint/1959

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